IBIS Macromodel Task Group Meeting date: 29 November 2022 Members (asterisk for those attending): Achronix Semiconductor: Hansel Dsilva Amazon: John Yan ANSYS: * Curtis Clark * Wei-hsing Huang Aurora Systems: Dian Yang Cadence Design Systems: * Ambrish Varma * Jared James Google: Hanfeng Wang GaWon Kim Intel: * Michael Mirmak * Kinger Cai Chi-te Chen Alaeddin Aydiner Keysight Technologies: Fangyi Rao Majid Ahadi Dolatsara Ming Yan Radek Biernacki Rui Yang Luminous Computing David Banas Marvell Steve Parker Mathworks (SiSoft): Walter Katz Mike LaBonte Micron Technology: * Randy Wolff Justin Butterfield Missouri S&T Chulsoon Hwang Yifan Ding Rivos Yansheng Wang SAE ITC Michael McNair Siemens EDA (Mentor): * Arpad Muranyi Teraspeed Labs: * Bob Ross Waymo: Zhiping Yang Zuken USA: * Lance Wang The meeting was led by Arpad Muranyi. Curtis Clark took the minutes. -------------------------------------------------------------------------------- Opens: - Arpad shared a list of the upcoming regularly scheduled meetings. After some discussion, the group expected to cancel the following meetings: - Dec 27, 2022 - Holidays - Jan 03, 2023 - Holidays - Jan 31, 2023 - week of DesignCon The group will also consider cancelling the Dec 20, 2022, meeting if the workload is sufficiently light. ------------- Review of ARs: - Kinger to send an update (draft4) of the PSIJ Sensitivity BIRD to the ATM list. - Done. -------------------------- Call for patent disclosure: - None. ------------------------- Review of Meeting Minutes: Arpad asked for any comments or corrections to the minutes of the November 22nd meeting. Randy moved to approve the minutes. Michael seconded the motion. There were no objections. -------------- New Discussion: Standard Power Integrity Model (SPIM) BIRD draft: Kinger said he had not received any feedback since the last meeting. He asked whether we should vote to submit it to the Open Forum soon. Arpad said there is no particular rush to send this to the Open Forum, as it likely won't go into IBIS 7.2 anyway. Kinger and Arpad asked people to review the draft and provide feedback. PSIJ Sensitivity BIRD: Kinger briefly reviewed the new draft (draft4). He noted modifications to the text explaining the PSIJ sensitivity envelope (now figure #7) and the data points provided in the [PSIJ Sensitivity] keyword, per the discussion at the previous meeting. Bob said the language still needs to be clarified. He said use of a cubic spline might be suggested but not required. He asked whether we should describe how to extrapolate beyond the frequency range of the data in the keyword. Randy said that we don't typically do that for other keywords, and the EDA tool can choose how it wants to fit/interpolate/extrapolate from the data in the keyword. Arpad noted that other keywords specify limits on the number of data points that can be provided, e.g., 100 for I/V tables and 1000 for V/T waveforms. Kinger said 100 should be sufficient for this keyword. Arpad said the keyword definition itself is straightforward and the columns of data are clearly defined. However, since this is frequency domain data, he asked for clarification on how it fits into IBIS SI/PI simulations, which are typically time domain simulations in which power supply fluctuations affect the output waveform of the buffer. Kinger said one goal of this proposal is to allow us to model the jitter contributions from the SI side and the PI side instead of assuming worst case scenarios for SI and PI. He said we could already run PDN simulations using current profiles (e.g., from the buffer model [Composite Current]s) to generate power supply noise waveforms. With these and the [PSIJ Sensitivity] data we could then compute the PSIJ contributions. Arpad summarized that the channel SI simulation would be done with an ideal power supply, and then the [PSIJ Sensitivity] data would be combined with the power supply noise waveforms, and the effects would be added into the SI waveform as a post-processing step. Kinger agreed with this flow. Kinger said that one power rail might power multiple interfaces. The IP designer knows the PSIJ effects of each power rail into each of the interfaces provided in the device. Each "circuit block" has one PSIJ table for the effects from each rail. The IP provider can generate final PSIJ sensitivity curves from each power rail to each interface and provide them in [PSIJ Sensitivity] keywords. Kinger said IP vendors can currently provide the current profiles in models. However, right now they only specify power supply noise requirements with a worst-case value such as < 10mV. We know the PSIJ Sensitivity is actually frequency dependent, and [PSIJ Sensitivity] allows the IP provider to provide the frequency dependent profile. It can be very expensive to overdesign a PDN to meet a conservative < 10mV value, and this new keyword would enable more realistic profiles and modeling and design decisions. Arpad asked whether this BIRD is intended to enable chip designers to provide PSIJ sensitivity information to board designers. Kinger said that might eventually be a use case, but for now he envisions IP designers providing this [PSIJ Sensitivity] data to chip designers. Chip designers need to holistically design the on-die PDN and the package, and this [PSIJ Sensitivity] would give them a more effective way to do that. For board/platform designers, the chip vendors would most likely provide the SPIM modeling information. That would be sufficient for most board designers. Arpad asked a higher-level question. He suggested that IBIS is generally perceived as a standard for board/platform designers using IBIS models from chip vendors. If the [PSIJ Sensitivity] keyword is largely for IP designers to provide information to chip vendors, does it belong in IBIS? Kinger said he thought it did belong in IBIS. He said that fundamentally, the active portions of IBIS Models represent the behavior of I/O buffers on the Silicon. Nowadays, the higher speeds have made package and interconnect more important, and we now provide S-parameter models for passive channels. However, IBIS has primarily been I/V and V/T curves representing I/O buffers on Silicon from day one. The [PSIJ Sensitivity] is extending that to represent the impacts on buffer jitter. Bob, Arpad and Kinger said discussion would continue next week. - Bob: Motion to adjourn. - Ambrish: Second. - Arpad: Thank you all for joining. ------------- Next meeting: 06 December 2022 12:00pm PT ------------- IBIS Interconnect SPICE Wish List: 1) Simulator directives